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M27V402
4 Mbit (256Kb x 16) Low Voltage UV EPROM and OTP EPROM
s
LOW VOLTAGE READ OPERATION: 3V to 3.6V FAST ACCESS TIME: 120ns LOW POWER CONSUMPTION: - Active Current 15mA at 5MHz - Standby Current 20A
40 40
s s
s s s
PROGRAMMING VOLTAGE: 12.75V 0.25V PROGRAMMING TIME: 100s/byte (typical) ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Device Code: 8Dh
1
1
FDIP40W (F)
PDIP40 (B)
DESCRIPTION The M27V402 is a low voltage, low power 4 Mbit UV erasable and electrically programmable EPROM, ideally suited for handheld and portable microprocessor systems requiring large programs. It is organized as 262,144 by 16 bits. The M27V402 operates in the read mode with a supply voltage as low as 3V. The decrease in operating power allows either a reduction of the size of the battery or an increase in the time between battery recharges. The FDIP40W (window ceramic frit-seal package) has a transparent lid which allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure. Table 1. Signal Names
A0-A17 Q0-Q15 E G VPP VCC VSS Address Inputs Data Outputs Chip Enable Output Enable Program Supply Supply Voltage Ground
PLCC44 (K)
TSOP40 (N) 10 x 20 mm
Figure 1. Logic Diagram
VCC
VPP
18 A0-A17
16 Q0-Q15
E G
M27V402
VSS
AI01819
May 1998
1/15
M27V402
Figure 2A. DIP Pin Connections
VPP E Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 VSS Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 G 1 40 2 39 3 38 4 37 5 36 6 35 7 34 8 33 9 32 10 31 M27V402 11 30 12 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21
AI01862
Figure 2B. LCC Pin Connections
VCC A17 A16 A15 A14 A13 A12 A11 A10 A9 VSS A8 A7 A6 A5 A4 A3 A2 A1 A0
Q12 Q11 Q10 Q9 Q8 VSS NC Q7 Q6 Q5 Q4
Q13 Q14 Q15 E VPP NC VCC A17 A16 A15 A14 1 44 A13 A12 A11 A10 A9 VSS NC A8 A7 A6 A5 12 M27V402 34 23 Q3 Q2 Q1 Q0 G NC A0 A1 A2 A3 A4
AI01820
Warning: NC = Not Connected.
Figure 2C. TSOP Pin Connections
A9 A10 A11 A12 A13 A14 A15 A16 A17 VCC VPP E DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 1 40 VSS A8 A7 A6 A5 A4 A3 A2 A1 A0 G DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VSS
For applications where the content is programmed only one time and erasure is not required, the M27V256 is offered in PDIP40, PLCC44 and TSOP40 (10 x 20 mm) packages. DEVICE OPERATION The operating modes of the M27V402 are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for VPP and 12V on A9 for Electronic Signature. Read Mode The M27V402 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time (tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of t GLQV from the falling edge of G, assuming that E has been low and the addresses have been stable for at least tAVQV-t GLQV.
10 11
M27V402 (Normal)
31 30
20
21
AI01821
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M27V402
Table 2. Absolute Maximum Ratings (1)
Symbol TA TBIAS TSTG VIO (2) VCC VA9 (2) VPP Parameter Ambient Operating Temperature (3) Temperature Under Bias Storage Temperature Input or Output Voltage (except A9) Supply Voltage A9 Voltage Program Supply Voltage Value -40 to 125 -50 to 125 -65 to 150 -2 to 7 -2 to 7 -2 to 13.5 -2 to 14 Unit C C C V V V V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum DC voltage on Input or Output is -0.5V with possible undershoot to -2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns. 3. Depends on range.
Table 3. Operating Modes
Mode Read Output Disable Program Verify Program Inhibit Standby Electronic Signature
Note: X = VIH or VIL, VID = 12V 0.5V.
E VIL VIL VIL Pulse VIH VIH VIH VIL
G V IL VIH VIH V IL VIH X V IL
A9 X X X X X X VID
VPP V CC or VSS V CC or VSS VPP VPP VPP V CC or VSS VCC
Q0-Q15 Data Out Hi-Z Data In Data Out Hi-Z Hi-Z Codes
Table 4. Electronic Signature
Identifier Manufacturer's Code Device Code A0 VIL VIH Q7 0 1 Q6 0 0 Q5 1 0 Q4 0 0 Q3 0 1 Q2 0 1 Q1 0 0 Q0 0 1 Hex Data 20h 8Dh
Standby Mode The M27V402 has a standby mode which reduces the supply current from 20mA to 20A with low voltage operation VCC 3.6V, see Read Mode DC
Characteristics table for details. The M27V402 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input.
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M27V402
Table 5. AC Measurement Conditions
High Speed Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 10ns 0 to 3V 1.5V Standard 20ns 0.4V to 2.4V 0.8V and 2V
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed 3V 1.5V 0V DEVICE UNDER TEST 2.0V 0.8V
AI01822
1N914
3.3k
Standard 2.4V
OUT CL
0.4V
CL = 30pF for High Speed CL = 100pF for Standard CL includes JIG capacitance
AI01823B
Table 6. Capacitance (1) (TA = 25 C, f = 1 MHz)
Symbol C IN COUT Parameter Input Capacitance Output Capacitance Test Condit ion VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF
Note: Sampled only, not 100% tested.
Two Line Output Control Because EPROMs are usually used in larger memory arrays, the product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur.
For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device.
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M27V402
Table 7. Read Mode DC Characteristics (1) (TA = 0 to 70C, -20 to 70C, -20 to 85C or -40 to 85C; VCC = 3.3V 10%; VPP = VCC)
Symbol ILI ILO ICC ICC1 ICC2 IPP VIL VIH (2) VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL Output High Voltage CMOS IOL = 2.1mA IOH = -400A IOH = -100A 2.4 VCC-0.7V Test Condition 0V VIN V CC 0V VOUT VCC E = VIL, G = VIL, IOUT = 0mA, f = 5MHz, VCC = 3.6V E = VIH E > VCC - 0.2V, VCC = 3.6V VPP = VCC -0.3 2 Min Max 10 10 20 1 20 10 0.8 VCC + 1 0.4 Unit A A mA mA A A V V V V V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Maximum DC voltage on Output is VCC +0.5V.
System Considerations The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of the transient current peaks is dependent on the output capacitive and inductive loading of the device. The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors. It is recommended that a 0.1F ceramic capacitor be used on every device between VCC and VSS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7F bulk electrolytic capacitor should be
used between VCC and VSS for every eight devices. The bulk capacitor should be located near the power supply connection point.The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces. Programming When delivered (and after each erasure for UV EPROM), all bits of the M27V402 are in the '1' state. Data is introduced by selectively programming '0's into the desired bit locations. Although only '0's will be programmed, both '1's and '0's can be present in the data word. The only way to change a '0' to a '1' is by die exposure to ultraviolet light (UV EPROM). The M27V402 is in the programming mode when VPP input is at 12.75V, G ia at VIH and E is pulsed to VIL. The data to be programmed is applied to 16 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. VCC is specified to be 6.25V 0.25V.
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M27V402
Table 8. Read Mode AC Characteristics (1) (TA = 0 to 70C, -20 to 70C, -20 to 85C or -40 to 85C; VCC = 3.3V 10%; VPP = VCC)
M27V402 Symbol Alt Parameter Test Condition -120 Min tAVQV tELQV tGLQV tEHQZ (2) tGHQZ (2) tAXQX tACC tCE tOE tDF tDF tOH Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition E = VIL, G = VIL G = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL 0 0 5 Max 120 120 60 50 50 0 0 0 -150 Min Max 150 150 80 50 50 0 0 0 -200 Min Max 200 200 100 50 50 ns ns ns ns ns ns Unit
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested.
Figure 5. Read Mode AC Waveforms
A0-A17 tAVQV E tGLQV G tELQV Q0-Q15
VALID tAXQX
tEHQZ
tGHQZ Hi-Z DATA OUT
AI00731
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M27V402
Table 9. Programming Mode DC Characteristics (1) (TA = 25 C; VCC = 6.25V 0.25V; VPP = 12.75V 0.25V)
Symbol ILI ICC IPP V IL VIH VOL VOH VID Parameter Input Leakage Current Supply Current Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL A9 Voltage IOL = 2.1mA IOH = -400A 2.4 11.5 12.5 E = VIL -0.3 2 Test Conditio n 0 V IN VCC Min Max 10 50 50 0.8 VCC + 0.5 0.4 Unit A mA mA V V V V V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
Table 10. Programming Mode AC Characteristics (1) (TA = 25 C; VCC = 6.25V 0.25V; VPP = 12.75V 0.25V)
Symbol tAVEL tQVEL tVPHEL t VCHEL tELEH tEHQX tQXGL tGLQV tGHQZ tGHAX Alt tAS tDS tVPS tVCS tPW tDH tOES tOE tDFP tAH Parameter Address Valid to Chip Enable Low Input Valid to Chip Enable Low VPP High to Chip Enable Low VCC High to Chip Enable Low Chip Enable Program Pulse Width Chip Enable High to Input Transition Input Transition to Output Enable Low Output Enable Low to Output Valid Output Enable High to Output Hi-Z Output Enable High to Address Transition 0 0 Test Condition Min 2 2 2 2 95 2 2 100 130 105 Max Unit s s s s s s s ns ns ns
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Sampled only, not 100% tested.
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M27V402
Figure 6. Programming and Verify Modes AC Waveforms
A0-A17 tAVEL Q0-Q15 DATA IN tQVEL VPP tVPHEL VCC tVCHEL E tELEH G
VALID
DATA OUT tEHQX
tGLQV
tGHQZ
tGHAX
tQXGL
PROGRAM
VERIFY
AI00730
Figure 7. Programming Flowchart
VCC = 6.25V, VPP = 12.75V
n=0
E = 100s Pulse NO ++n = 25 YES NO VERIFY YES Last Addr NO ++ Addr
FAIL
YES CHECK ALL WORDS 1st: VCC = 6V 2nd: VCC = 4.2V
AI00726C
PRESTO II Programming Algorithm PRESTO II Programming Algorithm allows the whole array to be programmed with a guaranteed margin, in a typical time of 26.5 seconds. Programming with PRESTO II consists of applying a sequence of 100s program pulses to each byte until a correct verify occurs (see Figure 7). During programming and verify operation, a MARGIN MODE circuit is automatically activated in order to guarantee that each cell is programmed with enough margin. No overprogram pulse is applied since the verify in MARGIN MODE at V CC much higher than 3.6V provides necessary margin to each programmed cell. Program Inhibit Programming of multiple M27V402s in parallel with different data is also easily accomplished. Except for E, all like inputs including G of the parallel M27V402 may be common. A TTL low level pulse applied to a M27V402's E input, with VPP at 12.75V, will program that M27V402. A high level E input inhibits the other M27V402s from being programmed. Program Verify A verify (read) should be performed on the programmed bits to determine that they were correctly programmed. The verify is accomplished with G at VIL, E at VIH, VPP at 12.75V and VCC at 6.25V.
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M27V402
On-Board Programming The M27V402 can be directly programmed in the application circuit. See the relevant Application Note AN620. Electronic Signature The Electronic Signature (ES) mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. The ES mode is functional in the 25C 5C ambient temperature range that is required when programming the M27V402. To activate the ES mode, the programming equipment must force 11.5V to 12.5V on address line A9 of the M27V402 with VPP=VCC=5V. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during Electronic Signature mode. Byte 0 (A0=VIL) represents the manufacturer code and byte 1 (A0=VIH) the device identifier code. For the STMicroelectronics M27V402, these two identifier bytes are given in Table 4 and can be read-out on outputs Q0 to Q7. ERASURE OPERATION (applies to UV EPROM) The erasure characteristics of the M27V402 is such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000A. It should be noted that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000A range. Research shows that constant exposure to room level fluorescent lighting could erase a typical M27V402 in about 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the M27V402 is to be exposed to these types of lighting conditions for extended periods of time, it is suggested that opaque labels be put over the M27V402 window to prevent unintentional erasure. The recommended erasure procedure for the M27V402 is exposure to short wave ultraviolet light which has a wavelength of 2537A. The integrated dose (i.e. UV intensity x exposure time) for erasure should be a minimum of 15 W-sec/cm2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with 12000 W/cm2 power rating. The M27V402 should be placed within 2.5 cm (1 inch) of the lamp tubes during the erasure. Some lamps have a filter on their tubes which should be removed before erasure.
9/15
M27V402
Table 11. Ordering Information Scheme
Example: Device Type Speed -120 = 120 ns -150 = 150 ns -200 = 200 ns Package F = FDIP40W B = PDIP40 K = PLCC44 N = TSOP40: 10 x 20mm Temperature Range 1 = -0 to 70C 4 = -20 to 70C 5 = -20 to 85C 6 = -40 to 85C Optio n TR =Tape & Reel Packing M27V402 -120 K 1 TR
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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M27V402
Table 12. FDIP40W - 40 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data
Symb A A1 A2 A3 B B1 C D D2 E E1 e eA eB L S N 7.62 2.54 14.99 48.26 15.24 1.45 0.51 3.91 3.89 0.41 - 0.23 51.79 - - 13.06 - - 16.18 3.18 1.52 - 4 40 2.49 - 11 0.300 mm Typ Min Max 5.72 1.40 4.57 4.50 0.56 - 0.30 52.60 - - 13.36 - - 18.03 0.100 0.590 1.900 0.600 0.057 0.020 0.154 0.153 0.016 - 0.009 2.039 - - 0.514 - - 0.637 0.125 0.060 - 4 40 0.098 - 11 Typ inches Min Max 0.225 0.055 0.180 0.177 0.022 - 0.012 2.071 - - 0.526 - - 0.710
Figure 8. FDIP40W - 40 pin Ceramic Frit-seal DIP, with window, Package Outline
A2
A3 A1 B1 B D2 D S
N 1
A L eA eB C
e
E1
E
FDIPW-a
Drawing is not to scale.
11/15
M27V402
Table 13. PDIP40 - 40 pin Plastic DIP, 600 mil width, Package Mechanical Data
Symb Typ A A1 A2 B B1 C D D2 E E1 e1 eA eB L S N 2.54 15.24 48.26 4.45 0.64 mm Min - 0.38 3.56 0.38 1.14 0.20 51.78 - 14.80 13.46 - - 15.24 3.05 1.52 0 40 Max - - 3.91 0.53 1.78 0.31 52.58 - 16.26 13.99 - - 17.78 3.81 2.29 15 0.100 0.600 1.900 Typ 0.175 0.025 inches Min - 0.015 0.140 0.015 0.045 0.008 2.039 - 0.583 0.530 - - 0.600 0.120 0.060 0 40 Max - - 0.154 0.021 0.070 0.012 2.070 - 0.640 0.551 - - 0.700 0.150 0.090 15
Figure 9. PDIP40 - 40 pin Plastic DIP, 600 mil width, Package Outline
A2 A1 B1 B D2 D S
N
A L eA eB C
e1
E1
1
E
PDIP
Drawing is not to scale.
12/15
M27V402
Table 14. PLCC44 - 44 lead Plastic Leaded Chip Carrier, square, Package Mechanical Data
mm Symb Typ A A1 A2 B B1 D D1 D2 E E1 E2 e F R N CP 0.89 1.27 Min 4.20 2.29 - 0.33 0.66 17.40 16.51 14.99 17.40 16.51 14.99 - 0.00 - 44 0.10 Max 4.70 3.04 0.51 0.53 0.81 17.65 16.66 16.00 17.65 16.66 16.00 - 0.25 - 0.035 0.050 Typ Min 0.165 0.090 - 0.013 0.026 0.685 0.650 0.590 0.685 0.650 0.590 - 0.000 - 44 0.004 Max 0.185 0.120 0.020 0.021 0.032 0.695 0.656 0.630 0.695 0.656 0.630 - 0.010 - inches
Figure 10. PLCC44 - 44 lead Plastic Leaded Chip Carrier, square, Package Outline D D1
1N
A1 A2
B1
Ne
E1 E
F 0.51 (.020)
D2/E2 B
e
1.14 (.045)
Nd
A R CP
PLCC
Drawing is not to scale.
13/15
M27V402
Table 15. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data
mm Symb Typ A A1 A2 B C D D1 E e L N CP 0.50 0.05 0.95 0.17 0.10 19.80 18.30 9.90 0.50 0 40 0.10 Min Max 1.20 0.15 1.05 0.27 0.21 20.20 18.50 10.10 0.70 5 0.020 0.002 0.037 0.007 0.004 0.780 0.720 0.390 0.020 0 40 0.004 Typ Min Max 0.047 0.006 0.041 0.011 0.008 0.795 0.728 0.398 0.028 5 inches
Figure 11. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
A1
L
Drawing is not to scale
14/15
M27V402
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (R) 1998 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://w ww.st.com
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